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 DDR Memory Modules
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  DDR Memory Modules / DDR2 RAM
1.Double data rate architecture, two data transfers per clock 2.bidrectional date strobe(DQS) 3.Differential clock inputs (CK and CK) 4.DLL aligns DQ and DQS transitions with CK transitions 5.Programmable burst length: 2, 4, 8 6.rogrammable/CAS latency (CL): 3 7.Programmable output driver strength: normal/weak refresh ,7.8us refresh intertval(8k/64ms refresh)

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1.2.5 V (SSTL-2 compatible) I/O for DDR I products,1.8Vpower supply for DDR II products 
2.Double-data-rate architecture, two data transfers per clock cycle 
3.Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver 
4.Data inputs and outputs are synchronized with DQS 
5.DQS is edge aligned with data for read, center aligned with data for write 
6.Differential clock inputs (CK and CK) 
7.DLL aligns DQ and DQS transitions with CK transitions 
8.Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS 
9.Four internal banks for concurrent operation (component) 
10.Data mask(DM) for write data 
11.Auto precharge option for each burst access 
12.Programmable burst length: 2, 4, 8 
13.Programmable/CAS latency (CL): 3 
14.Programmable output driver strength: normal/weak 
15.Refresh cycles: (8192 refresh cycles/64ms) 
16.7.8US maximum average periodic refresh interval 
17.Posted CAS by programmable additive latency for better command and data bus efficiency 
18.Off-chip-driver impedance adjustment and on-die-termination for better signal quality 
19.DQS can be disabled for single-ended data strobe operation 
20.2 variations of refresh 

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