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 DDR Memory Modules
 
 
Product Name:
  SDRAM memory
Catagory:
  DDR Memory Modules / SDRAM
Description:
*This document describes Value RAM's 64M x 64-bit (512MB) CL2.5 DDR400 SDRAM (Synchronous DRAM) memory module. * The components on this module include sixteen 32M x 8-bit (8M x 8-bit x 4 Bank) DDR400 SDRAM in TSOP packages. *This 184-pin DIMM uses gold contact fingers and requires +2.6V. * The electrical and mechanical specifications are as follows: * FEATURES: Clock Cycle Time (tCK) 5ns (min.) / 10ns (max.) * Row Cycle Time (tRC) 55ns (min.) Refresh Row Cycle Time (tRFC) 70ns (min.) Row Active Time (tRAS) 40ns (min.) / 100,000ns (max.) * Single Power Supply of +2.6V (+/- .1V) Power (IDD0) 3.100 W (operating) UL Rating 94 V – 0

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Details

Feature:
Capacity: 1GB DDR2 RAM
DDR Memory Type : DDR2
No. of Pins: 240 Pin
Module Type: LONG DIMM
Function: Non ECC Memory
Warranty: 5years

Detail Description:
DDR RAM.MEMORY MODULE, COMPUTER MEMORY
1.DDRII 533/667/800 MHz
2.168/184/240-pin socket type dual in line memory module (DIMM)
3.1.8V power supply
4.Data rate: 533/667/800Mbps (max.)
5.2.5 V (SSTL-2 compatible) I/O for DDR I products,1.8Vpower supply for DDR II products
6.Double-data-rate architecture, two data transfers per clock cycle
7.Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver
8.Data inputs and outputs are synchronized with DQS
9.DQS is edge aligned with data for read, center aligned with data for write
10.Differential clock inputs (CK and CK)
11.DLL aligns DQ and DQS transitions with CK transitions
12.Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS
13.Four internal banks for concurrent operation (component)
14.Data mask(DM) for write data
15.Auto precharge option for each burst access
16.Programmable burst length: 2, 4, 8
17.Programmable/CAS latency (CL): 3
18.Programmable output driver strength: normal/weak
19.Refresh cycles: (8192 refresh cycles/64ms)
20.7.8US maximum average periodic refresh interval
21.Posted CAS by programmable additive latency for better command and data bus efficiency
22.Off-chip-driver impedance adjustment and on-die-termination for better signal quality
23.DQS can be disabled for single-ended data strobe operation
24.2 variations of refresh
25.Auto refresh
26.Self refresh

Quality control:
1. IC chipset test
ICchipsets we utilizes are only top grade from original brands, like HY,Samsung, Elpida, etc. When new IC chipsets are received, we randomlychose samples for test, approximately 10% to 20% ratio, on profestionaltest software---RST. Only if the samples are all withouth problem, thisbatch of ICs can be sent to the next test;
2. SPD infomration test of the Module
Tocheck whether the SPD information is correct, we use two professionalsoftwares, CPU-Z and Sisoft Sandra 2007, to separately test the module.During this procedure, we subject to internationl stardard AQL to picksamples.
3. Compatibility test of the Module
Samples which arepicked according to AQL standard will be installed on more than 200 mainstream brands of motherboards, like Asus, Intel, etc.
4. Stability test
Picksamples according to AQL standard. Only after continous work WITHOUTCRASH for 48hours individually  at 70 degrees centigrade and -10degrees centigrade under big software like 3DMARKS, big games, etc, theModule can be sent out of the factory.

Order Term:
Price Term: EXW Shenzhen
Packing Term: retail or bulk packing
Payment Term: T/T and Western Union
Delivery Time: 2-3 working days
Warranty: 5 years
OEM and ODM are also available


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